Flexible Printed Circuit Board

ABSTRACT

A flexible printed circuit board comprises a conducting layer that includes a first signal line, a first ground plane and a second ground plane. A first shielding via extends from a third ground plane to a fourth ground plane and extends through the first ground plane to electrically connect the first ground plane, the third ground plane and the fourth ground plane. A second shielding via extends from the third ground plane to the fourth ground plane. The first ground plane, the second ground plane, the third ground plane, the fourth ground plane, the first shielding via and the second shielding via, together, circumferentially surround the first signal line to minimize electromagnetic interference with the first signal line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/961,406 filed Jul. 10, 2020, which is a national stage ofInternational Application No. PCT/US2019/013337 filed on Jan. 11, 2019,which claims priority to U.S. Provisional Patent Application No.62/616,821 filed Jan. 12, 2018 entitled “Flexible Printed CircuitBoard”, each of which is incorporated by reference herein in itsentirety.

FIELD OF THE INVENTION

The present invention generally relates to flexible printed circuitboard and, more particularly, to a flexible printed circuit board fortransmitting high frequency signals.

BRIEF SUMMARY OF THE INVENTION

A flexible printed circuit board is disclosed that comprises aconducting layer including a first signal line, a first ground plane anda second ground plane; a first ground plane layer including a thirdground plane; a second ground plane layer including a fourth groundplane; and a first shielding via extending from the third ground planeto the fourth ground plane and extending through the first ground planeto electrically connect the first ground plane, the third ground planeand the fourth ground plane; and a second shielding via extending fromthe third ground plane to the fourth ground plane and extending throughthe second ground plane to electrically connect the second ground plane,the third ground plane and the fourth ground plane, the first groundplane, the second ground plane, the third ground plane, the fourthground plane, the first shielding via and the second shielding via,together, circumferentially surrounding the first signal line tominimize electromagnetic interference with the first signal line.

In one aspect, the signal line is positioned between the first groundplane and the second ground plane.

In one aspect, the first signal line is positioned between the thirdground plane and the fourth ground plane.

In one aspect, the first signal line is positioned between the firstshielding via and the second shielding via.

In one aspect, the impedance of the first signal line is between 45 ohmsand 55 ohms.

In one aspect, the impedance of the first signal line is betweenapproximately 49 ohms and approximately 51 ohms.

In one aspect, the impedance of the first signal line is between 67.5ohms and 82.5 ohms.

In one aspect, the impedance of the first signal line is approximately75 ohms.

In one aspect, the impedance of the first signal line is between 90 ohmsand 110 ohms.

In one aspect, the impedance of the first signal line is approximately100 ohms.

In one aspect, the flexible printed circuit board comprises a firstdielectric plane positioned between the first signal line and the thirdground plane.

In one aspect, the first dielectric plane has a thickness of about 0.004inches.

In one aspect, the flexible printed circuit board comprises a seconddielectric plane positioned between the first signal line and the fourthground plane.

In one aspect, the second dielectric plane has a thickness of about0.003 inches.

In one aspect, a total thickness of the conducting layer, the firstground plane layer, the second ground plane layer, the first dielectricplane and the second dielectric plane is approximately 0.0094 inches.

In one aspect, the first ground plane, the second ground plane and thefirst signal line have a thickness of about 0.001 inches.

In one aspect, the third ground plane has a thickness of about 0.007inches.

In one aspect, the fourth ground plane has a thickness of about 0.007inches.

In one aspect, the flexible printed circuit board comprises a secondsignal line, a fifth ground plane and a sixth ground plane at theconducting layer, the second signal line being separate and distinctfrom the first signal line; a seventh ground plane at the first groundplane layer; an eighth ground plane at the second ground plane layer; athird shielding via extending from the seventh ground plane to theeighth ground plane and extending through the fifth ground plane toelectrically connect the fifth ground plane, the seventh ground planeand the eighth ground plane;

and a fourth shielding via extending from the seventh ground plane tothe eighth ground plane and extending through the sixth ground plane toelectrically connect the sixth ground plane, the seventh ground planeand the eighth ground plane, the fifth ground plane, the sixth groundplane, the seventh ground plane, the eighth ground plane, the secondshielding via and the third shielding via, together, circumferentiallysurrounding the second signal line to minimize electromagneticinterference with the second signal line.

In one aspect, the second shielding via and the third shielding via arepositioned between the first signal line and the second signal line.

In one aspect, the second ground plane and the fifth ground plane arepositioned between the first signal line and the second signal line.

In one aspect, the flexible printed circuit board comprises a dielectricplane positioned between the third ground plane and the seventh groundplane at the first ground plane layer to electromagnetically isolate thethird ground plane and the seventh ground plane.

In one aspect, the flexible printed circuit board comprises a dielectricplane positioned between the second ground plane and the fifth groundplane at the conducting layer to electromagnetically isolate the secondground plane and the fifth ground plane.

In one aspect, the flexible printed circuit board comprises a dielectricplane positioned between the fourth ground plane and the eighth groundplane at the second ground plane layer to electromagnetically isolatethe fourth ground plane and the eighth ground plane.

A method is disclosed for manufacturing a flexible printed circuitboard, the method comprises providing a conducting layer including afirst signal line, a first ground plane and a second ground plane;providing a first ground plane layer including a third ground plane;providing a second ground plane layer including a fourth ground plane;and stitching a first shielding via extending from the third groundplane to the fourth ground plane and extending through the first groundplane to electrically connect the first ground plane, the third groundplane and the fourth ground plane; and stitching a second shielding viaextending from the third ground plane to the fourth ground plane andextending through the second ground plane to electrically connect thesecond ground plane, the third ground plane and the fourth ground plane,the first ground plane, the second ground plane, the third ground plane,the fourth ground plane, the first shielding via and the secondshielding via, together, circumferentially surrounding the first signalline to minimize electromagnetic interference with the first signalline.

In one aspect, the method further comprises positioning the first signalline between the first ground plane and the second ground plane.

In one aspect, the method further comprises positioning the first signalline between the third ground plane and the fourth ground plane.

In one aspect, the method further comprises providing the first signalline between the first shielding via and the second shielding via.

In one aspect, the impedance of the first signal line is between 47.5ohms and 52.5 ohms.

In one aspect, the impedance of the first signal line is betweenapproximately 49 ohms and approximately 51 ohms.

In one aspect, the impedance of the first signal line is between 67.5ohms and 82.5 ohms.

In one aspect, the impedance of the first signal line is approximately75 ohms.

In one aspect, the impedance of the first signal line is between 90 ohmsand 110 ohms.

In one aspect, the impedance of the first signal line is approximately100 ohms.

In one aspect, the method further comprises providing a first dielectricplane between the first signal line and the third ground plane.

In one aspect, the first dielectric plane has a thickness of about 0.004inches.

In one aspect, the method further comprises providing a seconddielectric plane positioned between the first signal line and the fourthground plane.

In one aspect, the second dielectric plane has a thickness of about0.003 inches.

In one aspect, a total thickness of the conducting layer, the firstground plane layer, the second ground plane layer, the first dielectricplane and the second dielectric plane is approximately 0.0094 inches.

In one aspect, the first ground plane, the second ground plane and thefirst signal line have a thickness of about 0.001 inches.

In one aspect, the third ground plane has a thickness of about 0.007inches.

In one aspect, the fourth ground plane has a thickness of about 0.007inches.

In one aspect, the method further comprises providing a second signalline, a fifth ground plane and a sixth ground plane at the conductinglayer, the second signal line being separate and distinct from the firstsignal line; providing a seventh ground plane at the first ground planelayer; providing an eighth ground plane at the second ground planelayer; stitching a third shielding via extending from the seventh groundplane to the eighth ground plane and extending through the fifth groundplane to electrically connect the fifth ground plane, the seventh groundplane and the eighth ground plane; and stitching a fourth shielding viaextending from the seventh ground plane to the eighth ground plane andextending through the sixth ground plane to electrically connect thesixth ground plane, the seventh ground plane and the eighth groundplane, the fifth ground plane, the sixth ground plane, the seventhground plane, the eighth ground plane, the second shielding via and thethird shielding via, together, circumferentially surrounding the secondsignal line to minimize electromagnetic interference with the secondsignal line.

In one aspect, the method further comprises positioning the secondshielding via and the third shielding via between the first signal lineand the second signal line.

In one aspect, the method further comprises positioning the secondground plane and the fifth ground plane between the first signal lineand the second signal line.

In one aspect, the method further comprises positioning a dielectricplane between the third ground plane and the seventh ground plane at thefirst ground plane layer to electromagnetically isolate the third groundplane and the seventh ground plane.

In one aspect, the method further comprises positioning a dielectricplane between the second ground plane and the fifth ground plane at theconducting layer to electromagnetically isolate the second ground planeand the fifth ground plane.

In one aspect, the method further comprises positioning a dielectricplane between the fourth ground plane and the eighth ground plane at thesecond ground plane layer to electromagnetically isolate the fourthground plane and the eighth ground plane.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The foregoing summary, as well as the following detailed description ofembodiments of the invention, will be better understood when read inconjunction with the appended drawings of an exemplary embodiment. Itshould be understood, however, that the invention is not limited to theprecise arrangements and instrumentalities shown.

In the drawings:

FIG. 1 is a partial cross-section of a flexible printed circuit board,according to an exemplary embodiment of the invention;

FIG. 2 is a partial cross-section of a flexible printed circuit board,according to an exemplary embodiment of the invention;

FIG. 3A and 3B are flow charts of a method for manufacturing a flexibleprinted circuit board according to an exemplary embodiment of theinvention;

FIG. 4 is a partial cross-section of a flexible printed circuit board,according to an exemplary embodiment of the invention;

FIG. 5 is a conceptual top cross-section of a flexible printed circuitboard, according to an exemplary embodiment of the invention; and

FIG. 6 is a magnified view 6-6 of a portion of FIG. 5.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS OF THE INVENTION

In high frequency applications requiring a number of different radiofrequency (RF) signals, such as radio or video transmission systems,coaxial cables may be used as the signal lines. There are a number ofadvantages to using coaxial cables. For instance, coaxial cables may beused to minimize electromagnetic interference (i.e., crosstalk) betweensignal lines. However, to achieve these desired effects, the coaxialcables may be bulky, making them unsuitable for applications requiringcompact signal lines.

A flexible printed circuit board (FPCB) may be preferred over coaxialcable because the FPCB is more compact. An FPCB is a combination ofdifferent substrates laminated together to form an electrical circuit.However, to use an FPCB and maintain a compact design, the signal linesmust be placed in close proximity to one another. Unfortunately, whenthe signal lines on an FPCB are placed in close proximity to oneanother, there may be electromagnetic interference between the signallines that causes signal degradation. As such, there exists a need tohave a compact signal line configuration that also minimizeselectromagnetic interference. Tolerances may be easier to control whenprinting, or performing photolithography.

In one embodiment of the invention, an FPCB having multiple signal linesincludes one or more ground planes positioned around each signal line onthe same and/or different layers of the FPCB. The ground planes may beelectrically connected by stitching vias. Once the ground planes areelectrically connected, an electromagnetic shield (or Faraday cage) thatcircumferentially surrounds the signal line may be formed to protect thesignal line from electromagnetic interference from external sources.

Referring to the drawings in detail, wherein like reference numeralsindicate like elements throughout, there is shown in FIGS. 1-6,respectively, a flexible printed circuit board (FPCB) 10, and FPCB 20, amethod 30 for manufacturing a FPCB, a FPCB 40 and a cable 50, inaccordance with exemplary embodiments of the present invention.

FIG. 1 shows a cross-section of a FPCB 10, according to an exemplaryembodiment of the invention. The FPCB 10 may include a conductive layer100. The conductive layer 100 may include signal line 104, side groundplane 103 a and/or side ground plane 103 b.

The signal line 104 may be configured to transmit an electrical signal(e.g., an RF signal or a video signal). In some embodiments, theelectrical signal may exceed 100 MHz. At these frequencies, theelectrical signal may experience attenuation and reduction in signalquality as a result of exposure to any electromagnetic interference. Theelectromagnetic interference may have a greater effect at higherfrequency signals as compared to lower frequency signals. As usedherein, attenuation may refer to any reduction in the strength of asignal. The effects of attenuation and reduction in signal quality maybe mitigated by utilizing a FPCB with select materials used for eachlayer, and traces having tighter variances, such as trace width, traceheight and trace spacing as compared to co-axial cable.

Side ground plane 103 a and side ground plane 103 b may be positioned onopposite sides of the signal line 104. Side ground plane 103 a and/orside ground plane 103 b may be configured as an electro-magnetic shieldto electrically isolate signal line 104 from external sources (e.g.,other signal lines).

The signal line, side ground plane 103 a and/or side ground plane 103 bmay each be approximately 0.001 inches thick.

The FPCB 10 may include top ground plane 102 and/or bottom ground plane106. The top ground plane 102 and/or bottom ground plane 106 may beconfigured as an electro-magnetic shield to electrically isolate thesignal line 104 from external sources. Top ground plane 102 and/orbottom ground plane 106 may be flexible with a bend radius as tight as0.5 inches. Top ground plane 102 and/or bottom ground plane 106 may be0.5 oz. copper. Top ground plane 102 and/or bottom ground plane 106 maybe 1.0 oz. copper.

Side ground plane 103 a, side ground plane 103 b and signal line 104 maybe positioned between top ground plane 102 and bottom ground plane 106.

The FPCB 10 may include dielectric layer 101 and dielectric layer 105.Dielectric layer 101 and dielectric layer 105 may be configured toelectrically insulate signal line 104 from ground planes 102, 103 a, 103b, 106 to prevent short circuiting of the signal line 104. Dielectriclayer 101 and/or dielectric layer 105 may be an adhesive. Dielectriclayer 101 and/or dielectric layer 105 may be a flexible laminate.Dielectric layer 101 may be approximately 0.004 inches thick. Dielectriclayer 105 may be approximately 0.003 inches thick. The signal line 104may be positioned between dielectric layer 101 and dielectric layer 105.

The signal line 104, dielectric layer 101 and dielectric layer 105 maybe connected using an acrylic adhesive 107. The acrylic adhesive 107 maybe positioned between the signal line 104 and the side ground planes 103a and 103 b configured to electrically insulate signal line 104 from theside ground planes 103 a and 103 b. Via may be a shielding via orstitching via that extends between two or more layers and connects twoor more layers and may be used for shielding from electromagneticinterference or connecting ground planes as discussed in further detailbelow. In some embodiments, vias are formed after layers are formed(e.g., by drilling holes). In some embodiments, a cross-section of a viais circular, but in other embodiments the cross-section of a via may besquare or triangular.

The FPCB 10 may include shielding via 108 a and shielding via 108 b.Shielding via 108 a and/or shielding via 108 b may each be a segment ofconductive material that extends between two parallel layers toelectrically couple the layers together. Shielding via 108 a and/orshielding via 108 b may have a cross-sectional diameter of less than orequal to 0.100 inches, and in some embodiments 0.0078 inches. Shieldingvia 108 a and/or shielding via 108 b may have a cross-sectional diameterof less than 50% of the width of the narrowest layer that the via passesthrough. In some embodiments, shielding via 108 a and/or shielding via108 b may have a cross-sectional diameter between 0.100 inches and 0.050inches. In some embodiments, the shielding via 108 a may have adifferent cross-sectional diameter than the shielding via 108 b.Shielding via 108 a and/or shielding via 108 b may be generallyperpendicular to the two parallel layers that vias 108 a-b connect.Shielding via 108 a and/or shielding via 108 b may be inserted into theFPCB 10 after the layers are formed as discussed in further detailbelow. For example, shielding via 108 a and/or shielding via 108 b maybe stripline stitched into FPCB 10.

The FPCB 10 may include stitching via 130 a and/or stitching via 130 bthat may connect two or more ground systems to create a common groundbetween the two ground systems and thereby reduce phase variance betweentwo or more signal lines and/or prevent either of the ground systemsfrom acting as a transmission line segment themselves. Stitching via 130a and/or stitching via 130 b may be a segment of conductive materialthat extends between two parallel ground layers to electrically couplethe ground layers together. Stitching via 130 a and/or stitching via 130b may have a diameter of 0.100 inches, and in some embodiments 0.0078inches. Stitching via 130 a and/or stitching via 130 b may be generallyperpendicular to the two ground layers. Stitching via 130 a and/orstitching via 130 b may be inserted into the FPCB 10 after the layersare formed as discussed in further detail below. For example, stitchingvias 130 a-b may be stripline stitched into FPCB 10.

In some embodiments, the FPCB 10 may not include any shielding vias andstitching vias. In some embodiments, the FPCB 10 may include onlyshielding vias. In some embodiments, the FPCB 10 may include onlystitching vias.

Shielding via 108 a may be configured to electrically connect top groundplane 102, side ground plane 103 a and bottom ground plane 106 tosurround at least a portion of the signal line 104.

Shielding via 108 b may electrically connect top ground plane 102, sideground plane 103 b and bottom ground plane 106. Shielding via 108 aand/or shielding via 108 b may be flexible. Shielding via 108 a,shielding via 108 b, side ground plane 103 a, side ground plane 103 b,top ground plane 102, and/or bottom ground plane 106 maycircumferentially surround signal line 104 to minimize electromagneticinterference (e.g., cross-talk) between the signal line 104 and externalsources.

The FPCB 10 may include top interior cover layer 110 and bottom interiorcover layer 111. Top interior cover layer 110 and/or bottom interiorcover layer 111 may be configured to cover top ground plane 102, bottomground plane 106 and shielding vias 108 a, 108 b. Top interior coverlayer 110 and/or bottom interior cover layer 111 may be an acrylicadhesive. Top interior cover layer 110 and/or bottom interior coverlayer 111 may be 0.001 inches thick. The FPCB 10 may include topexterior cover layer 109 and bottom exterior cover layer 112. Topexterior cover layer 109 may be configured to cover top interior coverlayer 110. Bottom exterior cover layer 112 may be configured to coverbottom interior cover layer 111. Top exterior cover layer 109 and/orbottom exterior cover layer 112 may be a polyimide film (e.g., a KAPTONfilm). Top exterior cover layer 109 and/or bottom exterior cover layer112 may be 0.001 inches thick.

The FPCB 10 may include top prepreg layer 115 and bottom prepreg layer116. The basic material that may be needed to build a multi-layer boardmay include copper foil, prepreg (preimpregnated bonding sheet) andinner-layer cores. In some embodiments, a prepreg is a fibrous materialpreimpregnated with a particular synthetic resin, which may be used inmaking reinforced plastics. Top prepreg layer 115 and/or bottom prepreglayer 116 may be 0.005 inches thick. Top prepreg layer 115 may contacttop cover layer 109. Bottom prepreg layer 116 may contact bottom coverlayer 112. The FPCB 10 may include top laminate layer 113 and bottomlaminate layer 114. The top laminate layer 113 and bottom laminate layer114 may include a high performance FR406.008 0/H epoxy material. Toplaminate layer 113 and/or bottom laminate layer 114 may be 0.008 inchesthick. Top laminate layer 113 may contact top prepreg layer 115. Bottomlaminate layer 114 may contact bottom prepreg layer 116. The FPCB 10 mayinclude through vias 117, 118, 119 and 120. Through vias 117, 118, 119and 120 may include pads in corresponding positions on different layerof the FPCB 10 that may provide electrical connectivity betweenelements.

FIG. 2 shows a cross-section of an exemplary FPCB 20, according to oneembodiment of the invention. The FPCB 20 shown in FIG. 2 is similar tothe FPCB 10 shown in FIG. 1, but also includes an additional signal lineand corresponding structure as described below in more detail.

FPCB 20 may include a signal line 204, separate and distinct from signalline 104. The signal line 204 may be configured to transmit anelectrical signal (e.g., an RF signal or a video signal). In someembodiments, the electrical signal may exceed 100 MHz. In someembodiments of the invention, an FPCB 20 may include 4, 8, 16, 32, 64,and/or N signal lines, where N is an integer.

FPCB 20 may include side ground plane 203 a, side ground plane 203 b,top ground plane 202 and bottom ground plane 206. Side ground plane 203a, side ground plane 203 b, top ground plane 202 and/or bottom groundplane 206 may include similar features as side ground plane 103 a, sideground plane 103 b, top ground plane 102 and bottom ground plane 106,respectively.

In some embodiments, signal line 104 is electrically separated fromsignal line 204 by an inter-channel gap. In some embodiments, adielectric layer 210 may be positioned between top ground plane 102 andtop ground plane 202. In some embodiments, a dielectric layer 212 may bepositioned between side ground plane 103 b and side ground plane 203 a.In some embodiments, a dielectric layer 214 may be positioned betweenbottom ground plane 106 and bottom ground plane 206. In someembodiments, signal line 104 may be positioned between a dielectriclayers 231 a-b. In some embodiments, signal line 204 may be positionedbetween a dielectric layers 231 c-d.

FPCB 20 may include shielding via 208 a and/or shielding via 208 b.Shielding via 208 a and/or shielding via 208 b may include similarfeatures as shielding via 108 a and/or shielding via 108 b of FIG. 1,respectively. Side ground plane 203 a, side ground plane 203 b, topground plane 202, bottom ground plane 206, shielding via 208 a andshielding via 208 b may be configured to minimize electromagneticinterference between signal line 204 and external sources (e.g., signalline 104).

FPCB 20 may include stitching via 230 a and/or stitching via 230 b thatmay connect two or more ground systems to create a common ground betweenthe two ground systems and thereby reduce phase variance between two ormore signal lines and/or prevent either of the ground systems fromacting as a transmission line segment themselves. Stitching via 230 aand/or stitching via 130 b may include similar features as stitching via130 a and/or stitching via 130 b of FIG. 1, respectively.

In some embodiments, FPCB 20 includes a plurality of vias, includingshielding vias 208 a-b and stitching vias 230 a-b, spaced, and in someembodiments staggered, along an axial direction of the FPCB 20 on bothsides of the signal line 104. A distance between each via along theaxial direction may be based on, or a function of, a frequency of theelectrical signal propagating through signal line 204. In someembodiments, the distance between each via along the axial direction maybe inversely proportional to the frequency of the electrical signal,such that, as the frequency of the electrical signal increases, thedistance between each via along the axial direction may decrease.

In some embodiments, a rigid-flex printed circuit board may include FPCB20. The rigid-flex printed circuit board may include rigid ends. Therigid ends may include one or more plugs. FPCB 20 may be positioned inbetween the rigid ends of the rigid-flex printed circuit board.

In some embodiments, the FPCB 20 is configured to meet one or moredesign standards. Examples of design standards may include IPC-2221B,IPC-2223, IPC-4101E, IPC-4204B and IPC6013D, all of which areincorporated herein in their entireties.

IPC-2221B: Is the foundation design standard for all documents in theIPC-2220 series. This standard establishes the generic requirements forthe design of printed boards and other forms of component mounting orinterconnecting structures, whether single-sided, double-sided ormultilayer.

IPC-2223: Establishes the specific requirements for the design offlexible printed boards and forms of component mounting andinterconnecting structures. The flexible materials used in thestructures are comprised of insulating films, reinforced and/ornon-reinforced dielectric in combination with metallic materials.Revision D provides new design guidance and requirements for materialselection and construction, selective (button) plating, minimum bendingfor flexible circuits with overlay, impedance and capacitance control,unsupported edge conductors/fingers and copper filled vias/microvias.

IPC-4101E: Covers the requirement for base materials that are referredto as laminate or prepreg and listed in the specification sheets thatare contained in the last of the main body. These may be used primarilyfor rigid and multilayer printed boards for electronic interconnections.This document contains 65 individual specification sheets that can besearched using keywords. These keywords allow this document's user tofind materials of a similar nature, but with specific differingproperties that fine-tune their laminate and/or prepreg selection needs.

IPC-4204B: Establishes the classification system, the qualification andquality performance requirements for flexible metal-clad dielectricmaterials to be used for the fabrication of flexible printed boards.This standard encompasses 12 specification sheets that result from thecombinations of various copper foil claddings; a polymer base dielectricselected from polyesters, polyimides, liquid crystal polymers and atleast nine versions of polymer adhesives as well as adhesiveless bondingagents. The net result of these material combinations provide theindustry with suitable clad, flexible dielectrics for fabricatingflexible printed board interconnections. IPC-4204B also addresses how toutilize legacy designs that refer to earlier, out-of-date materialdesignations.

IPC-6013D: Covers qualification and performance requirements forflexible printed boards designed to IPC-2221 and IPC-2223. The flexibleprinted board may be single-sided, double-sided, multilayer orrigid-flex multilayer. All of these constructions may includestiffeners, PTHs, microvias, and blind/buried vias. IPC-6013Dincorporates new and updated requirements for final finishes,rigid-to-flex transition zones, deformation anomalies includingwrinkles, creases and soda strawing, marking, registration (annularring), conductor thickness reductions, dielectric removal in holes,resin smear, copper filled microvias and selective (button) hole plating

In one aspect, the FPCB 10 for transmitting high frequency signals maybe configured to minimize variations in impedance for discrete targets.Examples of impedance targets may include 50 ohms, 75 ohms, and/or 100ohms. Selection of an impedance target may be based on attenuation,power and voltage requirements. In some embodiments, the FPCB 10 may beconfigured to maintain impedance values of 50 ohms +/−10%, 75 ohms+/−10%, and 100 ohms +/−10%.

In one aspect, the FPCB 10 for transmitting high frequency signals maybe configured to maintain the electrical (phase) length of the flexcable to within a target of (+/−) 1 electrical degree across a range offrequencies (e.g., 67 to 300 MHz frequencies). The phase length orelectrical length of a cable (flex, coax, etc.) may depend upon severalfactors including material composition and construction.

There are serval types of phase matching requirements and associatedtolerances, typically utilized in the FPCB 10. Examples include:

-   -   Relative Phase: Phase matched in sets—All the cable assemblies        are matched to each other.    -   Absolute Phase: Phase matched to an electrical length—As with a        mechanical standard, this electrical length in degrees or time        is determined by the customer.    -   Phase matched to a standard: All of the cables are matched to a        standard. This standard may have been established from a        previous lot or provided by the customer.    -   Phased offset matching: One or more cables are provided with a        defined phase offset compared to each of the other cable        assemblies.

In one aspect, the FPCB 10 may minimize the variations in velocitypropagation to achieve a desired phase match. In one aspect, the FPCB 10may be a delivery system that provides precision and control of phaselength for parallel transmission lines while adhering to regulatoryguidelines.

FIGS. 3A and 3B illustrate a method 30 for manufacturing a FPCB (e.g.,FPCB 10) according to an exemplary embodiment of the invention.

In steps 301-315 flexible layers 2-4 may be laminated together anddrilled. Via (e.g., stitching vias or shielding vias) holes may beplated.

In step 301, a flexible copper clad laminate (FCCL) may be baked. Insome embodiments, the FCCL may be dielectric layer 101. In someembodiments the FCCL may be dielectric layer 106.

In step 302, the FCCL may be chemical cleaned and micro-etched.

In step 303, the FCCL may laminate photoresist, expose and develop.

In step 304, the FCCL may be etched and photoresist stripped.

In step 305, an automatic optical inspection may be performed.

In step 306, the bondply may be fabricated. Layers 2 and 4 may belaminated with bondply. In some embodiments, layer 2 may be dielectriclayer 101 and layer 4 may be dielectric layer 105.

In step 306 a, bondply may be fabricated by sheeting. In someembodiments, bondply may be top ground plane 102 or bottom ground plane106.

In step 306 b, bondply may be laser routed, drilled or die cut.

In step 307, vias may have holes that may be drilled, deburred andplasma treated.

In step 308, stitching holes may be metalized.

In step 309, vias may be cleaned and microetched.

In step 310 vias may be laminated, printed and photoplating resist maybe developed.

In step 311, photoresist may be plated and metal etched into holes.

In step 312, photo plating resist may be stripped.

In step 313, base copper may be etched.

In step 314, sacrificial metal etch resist may be stripped.

In step 315, cover layers may be fabricated for layers 2 and 4. Thecover layers may be laminated onto layers 2 and 4. In some embodiments,the cover layers may be cover layers 109-112.

In step 315 a, cover layers 2 and 4 may be sheeted.

In step 315 b, cover layers 2 and 4 may be laser routed, drilled and diecut.

In step 316-321, the hardboard layers 1 and 5 may be fabricated. In someembodiments hardboard layers 1 and 5 are top laminate layer 113 andbottom laminate layer 114, respectively.

In step 316, the hardboard layers 1 and 5 may be glass reinforced copperclad laminate that may be baked.

In step 317, the hardboard layers 1 and 5 may be chemical cleaned andmicroeteched.

In step 318, the photoresist may be laminated, exposed and developed.

In step 319, copper may be etched and photoresist may be stripped.

In step 320, automatic optical inspection of the hardboard layers 1 and5 may be performed.

In step 321, the windows may be routed for flexible areas of FPCB.

In step 322, the prepreg layers may be fabricated by routing windows inno flow prepreg. In some embodiments, the prepreg layers are top prepreglayer 115 and bottom prepreg layer 116.

In steps 323-343, the rigid-flex printed circuit board may be assembled.

In step 323, the inner layers 2-4 may be oxidize treated. In someembodiments, inner layers are labeled as 101-112 in FIG. 1.

In step 324, the flexible layers, laminate and no flow prepreg may becombined. In some embodiments the flexible layers are layers 2-4. Insome embodiments the laminate layers are top laminate 113 and bottomlaminate 114. In some embodiments the prepreg layers are top prepreglayer 115 and bottom prepreg layer 116.

In step 325, a final lamination may be performed.

In step 326, through vias may be drilled, deburred and plasma treated.In some embodiments through vias are through vias 117-120.

In step 327, through via holes may be metallized.

In step 328, copper may be cleaned and microetched.

In step 329, photo plating resist may be laminated, printed anddeveloped.

In step 330, copper and sacrificial metal etch resist may be patternplated.

In step 331, resist may be strip plated.

In step 332, base copper may be drilled with non-plated holes andetched.

In step 333, copper and sacrificial metal etch resist may be stripped.

In step 334, through vias may be cleaned, solder mask applied, exposedand developed.

In step 335, the FPCB may be baked.

In step 336, nomenclature may be applied.

In step 337, the FPCB may be baked.

In step 338, a Electroless Nickel Immersion Gold (ENIG) finish appliedto the FPCB.

In step 339, the FPCB may have final microsection performed.

In step 340, flexible areas may be laser routed.

In step 341, hardboard areas may be mechanical routed.

In step 342, the FPCB may undergo a final inspection and electricaltest.

In step 343, the FPCB may be packed and ready for shipment.

Referring now to FIG. 4, there is shown a cross-section of an FPCB 40,according to an exemplary embodiment of the invention.

In some embodiments, the FPCB 40 may forego including vias, such as vias108 a-b of FPCB 10 of FIG. 1. In these embodiments, ground traces of theFPCB 40 are sufficiently wide and a thickness of the dielectric layersare sufficiently thin to achieve EMI shielding. In some embodiments, theground traces may be less than or equal to 0.045 inches. In someembodiments, one or more dielectric layers have a thickness of less thanor equal to 0.001 inches.

The FPCB 40 may include a conductive layer 400. The conductive layer 400may include a copper layer 402 with a width of 0.001 inches. Theconductive layer 400 may include signal line 404, side ground plane 403a and/or side ground plane 403 b. In some embodiments, the conductivelayer 400 may include a plurality of signal lines and side groundplanes, similar to signal line 404, side ground plane 403 a and/or sideground plane 403 b. The signal line 404 may be configured to transmit anelectrical signal (e.g., an RF signal or a video signal). In someembodiments, the electrical signal may exceed 100 MHz. The signal line404 may have a width of approximately 0.0039 inches. Side ground plane403 a and/or side ground plane 403 b may have a width that isapproximately 10 times the width of the signal line 404. In someembodiments, side ground plane 403 a and/or side ground plane 403 b mayhave a width of approximately 0.045 inches. Side ground plane 403 aand/or side ground plane 403 b may be positioned on opposite sides ofthe signal line 404 and may be configured as an electro-magnetic shieldto electrically isolate signal line 404 from external sources (e.g.,other signal lines). A distance between the signal line 404 and the sideground plane 403 a or the side ground plane 403 b is approximately0.0153 inches. A portion of the copper layer 402 may be disposed betweenthe signal line 404 and the side ground plane 403 a or the side groundplane 403 b and may have a width of 0.0153 inches. Side ground plane 403a and side ground plane 403 b may have a width of 0.0055 inches. Anotherportion of the copper layer 402 may be positioned outside of the sideground plane 403 a or the side ground plane 403 b and may have a widthof approximately 0.0145 inches. The signal line 404, side ground plane403 a and/or side ground plane 403 b may be approximately 0.001 inchesthick.

The FPCB 40 may include a top dielectric layer 401 and a bottomdielectric layer 405. Top dielectric layer 401 and bottom dielectriclayer 105 may be configured to electrically insulate signal line 404from other ground planes prevent short circuiting of the signal line404. Top dielectric layer 401 may have a width of 0.003 inches. Bottomdielectric layer 405 may have a width of 0.005 inches. Top dielectriclayer 401 and/or bottom dielectric layer 405 may include a film layer.In another embodiment, top dielectric layer 401 may be approximately0.004 inches thick. In another embodiment, bottom dielectric layer 405may be approximately 0.003 inches thick. Top dielectric layer 401 and/orbottom dielectric layer 405 may be an adhesive. Top dielectric layer 401and/or bottom dielectric layer 405 may be a flexible laminate.

The conductive layer 400 may be positioned between dielectric layer 401and dielectric layer 405. The conductive layer 400 and top dielectriclayer 401 may be connected using an acrylic adhesive 407. The acrylicadhesive 407 may be positioned between the conductive layer 400 and topdielectric layer 401 to adhere the conductive layer 400 to thedielectric layer 405. The acrylic adhesive 407 may be 0.002 inchesthick.

The FPCB 40 may include a top copper layer 420 disposed above thedielectric layer 401. The copper layer 420 may include a top space 414and/or top space 406. The FPCB 40 may include a bottom copper layer 422.The bottom copper layer 422 may include a bottom space 413 and/or bottomspace 408. In some embodiments, top space 414, top space 406, bottomspace 413 and/or bottom space 408 may each have a width of 0.0045inches. The space or spacing may affect the electrical properties of theFPCB. The spacing and material may control impedance, capacitance,attenuation and other electrical properties of the FPCB 40. For example,by changing or adjusting the spacing, impedance, capacitance,attenuation and other electrical properties of the FPCB 40 may alsochange. Side ground plane 403 a, side ground plane 403 b, top copperlayer 420, and/or bottom copper layer 422 may circumferentially surroundsignal line 404 to minimize electromagnetic interference between thesignal line 404 and external sources.

The FPCB 40 may include top interior cover layer 410 and bottom interiorcover layer 411. Top interior cover layer 410 and/or bottom interiorcover layer 411 may be configured to cover top copper layer 420 and/orbottom copper layer 422, respectively. Top interior cover layer 410and/or bottom interior cover layer 411 may be an acrylic adhesive. Topinterior cover layer 410 and/or bottom interior cover layer 411 may be0.001 inches thick.

The FPCB 10 may include top exterior cover layer 409 and bottom exteriorcover layer 412. Top exterior cover layer 409 may be configured to covertop interior cover layer 410. Bottom exterior cover layer 412 may beconfigured to cover bottom interior cover layer 411. Top exterior coverlayer 409 and/or bottom exterior cover layer 412 may be a polyimide film(e.g., a KAPTON film). Top exterior cover layer 409 and/or bottomexterior cover layer 412 may be 0.001 inches thick.

In some embodiments, an FPCB 40 may include 2, 4, 8, 16, 32, 64, and/orN signal lines, where N is an integer. In these embodiments, at leastsome portion of the FPCB 40 is repeated for each signal line andattached to the right or left side of the FPCB 40, separated by spaces(e.g., spaces 406, 408, 413, 414).

Referring now to FIG. 5, there is shown a top cross-section of a cable50 along A to A′ of FIG. 4, according to an exemplary embodiment of theinvention. While the cable 50 is illustrating the FPCB 40 of FIG. 4, thecable 50 may include other FPCBs, including FPCB 10 and FPCB 20. Thecable 50 may include a first connector 502 and/or a second connector504. The cable 50 may include one or more signals lines (e.g., signalline 404) and/or guard traces (e.g., ground traces 403 a-b) that extendfrom the first connector 502 to the second connector 504. The firstconnector 502 and/or the second connector 504 may be a rigid printedcircuit board. The first connector 502 and/or the second connector 504may include one or more connector elements (e.g., pins, wires, contacts,zero insertion force connectors, etc.) that electrically couple thecable 50 to an external electrical device, such that when the firstconnector 502 and the second connector 504 is connected to first andsecond external devices, respectively, an electrical signal may passthrough the cable 50 from the first external device to the secondexternal device.

Each of the signal lines, and/or guard traces may be centered on, andperpendicular to, a connector pitch. As used herein, connector pitch mayrefer to the center line extending between at least two connectorcontacts (e.g., contacts 505 a-b as shown in FIG. 6) of the connector(e.g., second connector 504).

In some embodiments, connector pitch, shielding and retention featuresmay be based on system design and application. In some embodiments, apitch of the one or more signal lines and a pitch of the one or moreguard traces may be uniform. The pitch of the one or more signals linesand/or one or more guard traces are based on connector, impedance,dielectric strength and/or current carrying requirements of theapplication. In some embodiments, the cable 50 may include staggeredvias to connect guard traces with top and bottom ground planes (as shownin FIGS. 1, 2 and 4). The guard traces are implemented as isolatedground planes on both top and bottom layers of the FPCB to separate eachsignal line, maintain electromagnetic communication between externaldevices and minimize crosstalk. In some embodiments, the cable 50 mayinclude ground plane loops (e.g., loop 506 as shown in FIG. 6) tofurther isolate the signal lines (e.g., signal line 504) by surroundingthe respective signal lines in a semi-circle or arc and thereby provideintra-contact cross talk shielding. In some embodiments, connector 502and/or connector 504 may be coupled to one or more ground planes toshield the connector from electromagnetic interference.

In one embodiment, spacing between one or more shielding via 108 a andshielding via 108 b has been calculated to minimize ground effects whilemaximizing manufacturability. Shielding via stitching lengths may beless than or equal to ¼ wavelength; less than or equal to 1/8wavelength; or less than or equal to 1/20 wavelength. In one embodiment,the wavelength is equal to approximately 60% of the free-space velocityfor electromagnetic radiation propagating through the FPCB dielectrics(commonly measured and referred to as the velocity of propagation)divided by the application fundamental frequency.

In some embodiments, the cable 50 may include a signal line having a50-ohm impedance. The signal line may have a width of 0.004 inches and aheight of 0.005 inches (e.g., approximately 36 AWG). The cable 50 mayinclude a layer of 0.5 oz. copper. The cable 50 may include a pitch of0.5 mm.

When two signals are transmitted across the cable 50, due to variationsin the materials, spacing, length width of traces due to manufacturingdefects, the signals will be out of phase. To reduce the phasediscrepancy, the variations in materials, spacing, length width oftraces are minimized such that impedances between the signals aresimilar causing the electrical lengths to be similar such that thesignals are within one electrical degree of each other. An electricaldegree may refer to 1/360th of a cycle of the signal traversing thesignal lines. Electrical length may refer to the number of wavelengthsof a signal required to traverse a signal line of a cable having aphysical length.

As explained above, due to manufacturing process variation of the cable50, the electrical lengths may be different for signal lines. In someembodiments, the physical length of the FPCB of the cable for at leastone signal line may be adjusted (e.g., lengthened, or utilized withdelay circuitry or equalization circuitry) so that electrical lengthsfor at least two signal lines on the cable 50 are substantially similar.For certain RF applications the two signal lines may be substantiallysimilar if the two signal lines are at least one of: within severalelectrical degrees of each of the two signal lines. Adjusting thephysical length of the FPCB to reduce variance in the electrical lengthbetween signal lines to within several electrical degrees is a morecontrolled manufacturing process with FPCB than coaxial cable.

Alternative Embodiments

In some embodiments, a flexible printed circuit board (e.g., FPCB 10)may comprise a conducting layer (e.g., conducting layer 100) which mayinclude a first signal line (e.g., signal line 104), a first groundplane (e.g., ground plane 103 a) and a second ground plane (e.g., groundplane 103 b). A first ground plane layer (e.g., ground plane layer 120)may include a third ground plane (e.g., ground plane 102). A secondground plane layer (e.g., ground plane layer 122) may include a fourthground plane (e.g., ground plane 106). A first shielding via (e.g.,shielding via 108 a) may extend from the third ground plane to thefourth ground plane through the first ground plane to electricallyconnect the first ground plane, the third ground plane and the fourthground plane. A second shielding via (e.g., shielding via 108 b) mayextend from the third ground plane to the fourth ground plane throughthe second ground plane to electrically connect the second ground plane,the third ground plane and the fourth ground plane. The first groundplane, the second ground plane, the third ground plane, the fourthground plane, the first shielding via and the second shielding via,together, may circumferentially surround the first signal line tominimize electromagnetic interference with the first signal line.

In some embodiments, the signal may be positioned between the firstground plane and the second ground plane. In some embodiments, the firstsignal line may be positioned between the third ground plane and thefourth ground plane. In some embodiments, the signal line may bepositioned between the first shielding via and the second shielding via.

In some embodiments, the impedance of the first signal line may bebetween 47.5 ohms and 52.5 ohms. In some embodiments, the impedance ofthe first signal line may be between 49 ohms and 51 ohms. In otherembodiments, the impedance of the first signal line may be between 45 to55 ohms, with a targeted center of the distribution at 50 ohms. In oneaspect, the impedance of the first signal line is between 67.5 ohms and82.5 ohms. In one aspect, the impedance of the first signal line isapproximately 75 ohms. In one aspect, the impedance of the first signalline is between 90 ohms and 110 ohms. In one aspect, the impedance ofthe first signal line is approximately 100 ohms. By using an FPCB withcertain materials used for each layer, and by using photolithography,tighter geometries such as trace width variance, trace height varianceand trace spacing variance can be achieved, which minimize variance inimpedance and result in better signal quality as compared to coaxialcable.

In some embodiments, the flexible printed circuit board furthercomprises a first dielectric plane (e.g., dielectric plane 101)positioned between the signal line and the third ground plane. In someembodiments, the first dielectric plane has a thickness of about 0.004inches. In some embodiments, the flexible printed circuit board furthercomprises: a second dielectric plane (e.g., dielectric plane 105)positioned between the signal line and the fourth ground plane. In someembodiments, the second dielectric plane has a thickness of about 0.003inches. In some embodiments, a total thickness of the conducting layer,the first ground plane layer, the second ground plane layer, the firstdielectric plane and the second dielectric plane is approximately 0.0094inches. In some embodiments, the first ground plane, the second groundplane, and the first signal line have a thickness of about 0.001 inches.In some embodiments, the third ground plane may have a thickness ofabout 0.007 inches. In some embodiments, the fourth ground plane mayhave a thickness of about 0.007 inches.

In some embodiments, the flexible printed circuit board may include asecond signal line (e.g., signal line 204), a fifth ground plane (e.g.,ground plane 203 a) and a sixth ground plane (e.g., ground plane 203 b)at the conducting layer (e.g., conducting layer 100), the second signalline being separate and distinct from the first signal line. Theflexible printed circuit board may include a seventh ground plane (e.g.ground plane 202) at the first ground plane layer. The flexible printedcircuit board of may include an eighth ground plane (e.g., ground plane206) at the second ground plane layer. The flexible printed circuitboard of may include a third shielding via (e.g., shielding via 208 a)extending from the seventh ground plane to the eighth ground plane andextending through the fifth ground plane to electrically connect thefifth ground plane, the seventh ground plane and the eighth groundplane. The flexible printed circuit board may include a fourth shieldingvia (e.g., shielding via 208 b) extending from the seventh ground planeto the eighth ground plane and extending through the sixth ground planeto electrically connect the sixth ground plane, the seventh ground planeand the eighth ground plane. In some embodiments, the fifth groundplane, the sixth ground plane, the seventh ground plane, the eighthground plane, the second shielding via and the third shielding via,together, circumferentially surrounding the second signal line tominimize electromagnetic interference with the second signal line.

In some embodiments, the second shielding via and the third shieldingvia are positioned between the first signal line and the second signalline. In some embodiments, the second ground plane and the fifth groundplane are positioned between the first signal line and the second signalline. In some embodiments, the flexible printed circuit board, furthercomprises a dielectric plane (e.g., dielectric plane 210) positionedbetween the third ground plane and the seventh ground plane at the firstground plane layer to electromagnetically isolate the third ground planeand the seventh ground plane. In some embodiments, the flexible printedcircuit board, further comprises a dielectric plane (e.g., dielectricplane 212) positioned between the second ground plane and the fifthground plane at the conducting layer to electromagnetically isolate thesecond ground plane and the fifth ground plane. In some embodiments, theflexible printed circuit board, further comprises a dielectric plane(e.g., dielectric plane 214) positioned between the fourth ground planeand the eighth ground plane at the second ground plane layer toelectromagnetically isolate the fourth ground plane and the eighthground plane.

In some embodiments, a method for manufacturing a flexible printedcircuit board (e.g., FPCB 10), comprises: providing a conducting layer(e.g., conducting layer 100) including a first signal line (e.g., signalline 104), a first ground plane (e.g., side ground plane 103 a) and asecond ground plane (e.g., side ground plane 103 b). The method maycomprise providing a first ground plane layer (e.g., ground plane layer120) including a third ground plane (e.g., top ground plane 102). Themethod may comprise providing a second ground plane layer (e.g., bottomground plane layer 122) including a fourth ground plane (e.g., bottomground plane 106). The method may comprise stitching a first shieldingvia (e.g., shielding via 108 a) extending from the third ground plane tothe fourth ground plane and extending through the first ground plane toelectrically connect the first ground plane, the third ground plane andthe fourth ground plane. The method may comprise stitching a secondshielding via (e.g., shielding via 108 b) extending from the thirdground plane to the fourth ground plane and extending through the secondground plane to electrically connect the second ground plane, the thirdground plane and the fourth ground plane. The first ground plane, thesecond ground plane, the third ground plane, the fourth ground plane,the first shielding via and the second shielding via, together, maycircumferentially surround the first signal line to minimizeelectromagnetic interference with the first signal line.

It will be appreciated by those skilled in the art that changes could bemade to the exemplary embodiments shown and described above withoutdeparting from the broad inventive concept thereof. It is understood,therefore, that this invention is not limited to the exemplaryembodiments shown and described, but it is intended to covermodifications within the spirit and scope of the present invention asdefined by the claims. For example, specific features of the exemplaryembodiments may or may not be part of the claimed invention and featuresof the disclosed embodiments may be combined. Unless specifically setforth herein, the terms “a”, “an” and “the” are not limited to oneelement but instead should be read as meaning “at least one”. As usedherein, the term “about” or “approximately” may refer to + or −10% ofthe value referenced. For example, “about 9” is understood to encompass8.2 and 9.9.

It is to be understood that at least some of the figures anddescriptions of the invention have been simplified to focus on elementsthat are relevant for a clear understanding of the invention, whileeliminating, for purposes of clarity, other elements that those ofordinary skill in the art will appreciate may also comprise a portion ofthe invention. However, because such elements are well known in the art,and because they do not necessarily facilitate a better understanding ofthe invention, a description of such elements is not provided herein.

Further, to the extent that the method does not rely on the particularorder of steps set forth herein, the particular order of the stepsshould not be construed as limitation on the claims. The claims directedto the method of the present invention should not be limited to theperformance of their steps in the order written, and one skilled in theart can readily appreciate that the steps may be varied and still remainwithin the spirit and scope of the present invention.

1. A flexible printed circuit board, comprising: a conducting layerincluding a first signal line, a first ground plane and a second groundplane; a first ground plane layer including a third ground plane; asecond ground plane layer including a fourth ground plane; and a firstshielding via extending from the third ground plane to the fourth groundplane and extending through the first ground plane to electricallyconnect the first ground plane, the third ground plane and the fourthground plane; and a second shielding via extending from the third groundplane to the fourth ground plane and extending through the second groundplane to electrically connect the second ground plane, the third groundplane and the fourth ground plane, the first ground plane, the secondground plane, the third ground plane, the fourth ground plane, the firstshielding via and the second shielding via, together, circumferentiallysurrounding the first signal line to minimize electromagneticinterference with the first signal line.
 2. The flexible printed circuitboard of claim 1, wherein the first signal line is positioned betweenthe first ground plane and the second ground plane.
 3. The flexibleprinted circuit board of claim 1, wherein the first signal line ispositioned between the third ground plane and the fourth ground plane.4. The flexible printed circuit board of claim 1, wherein the firstsignal line is positioned between the first shielding via and the secondshielding via.
 5. (canceled)
 6. (canceled)
 7. The flexible printedcircuit board of claim 1, further comprising: a first dielectric planepositioned between the first signal line and the third ground plane. 8.The flexible printed circuit board of claim 1, further comprising: asecond dielectric plane positioned between the first signal line and thefourth ground plane.
 9. The flexible printed circuit board of claim 1,further comprising: a second signal line, a fifth ground plane and asixth ground plane at the conducting layer, the second signal line beingseparate and distinct from the first signal line; a seventh ground planeat the first ground plane layer; an eighth ground plane at the secondground plane layer; a third shielding via extending from the seventhground plane to the eighth ground plane and extending through the fifthground plane to electrically connect the fifth ground plane, the seventhground plane and the eighth ground plane; and a fourth shielding viaextending from the seventh ground plane to the eighth ground plane andextending through the sixth ground plane to electrically connect thesixth ground plane, the seventh ground plane and the eighth groundplane, the fifth ground plane, the sixth ground plane, the seventhground plane, the eighth ground plane, the second shielding via and thethird shielding via, together, circumferentially surrounding the secondsignal line to minimize electromagnetic interference with the secondsignal line.
 10. (canceled)
 11. (canceled)
 12. The flexible printedcircuit board of claim 9, further comprising a dielectric planepositioned between the third ground plane and the seventh ground planeat the first ground plane layer to electromagnetically isolate the thirdground plane and the seventh ground plane.
 13. The flexible printedcircuit board of claim 9, further comprising a dielectric planepositioned between the second ground plane and the fifth ground plane atthe conducting layer to electromagnetically isolate the second groundplane and the fifth ground plane.
 14. The flexible printed circuit boardof claim 9, further comprising a dielectric plane positioned between thefourth ground plane and the eighth ground plane at the second groundplane layer to electromagnetically isolate the fourth ground plane andthe eighth ground plane. 15-28. (Canceled)
 29. A flexible printedcircuit board including: a conducting layer including a first signalline and a second signal, the first signal line having a first physicallength and a first electrical length and the second signal line having asecond physical length and a second electrical length, the physicallength of the first signal line being different from the physical lengthof the second signal line such that a difference between the firstelectrical length and the second electrical length is less than oneelectrical degree.
 30. The flexible printed circuit board of claim 29,wherein the physical length of the first signal line being differentfrom the physical length of the second signal line such that adifference between the first electrical length and the second electricallength is less than one-half of an electrical degree.
 31. The flexibleprinted circuit board of claim 29, wherein the physical length of thefirst signal line being different from the physical length of the secondsignal line such that a difference between the first electrical lengthand the second electrical length is less than one-quarter of anelectrical degree.
 32. The flexible printed circuit board of claim 29,wherein the conducting layer includes: a first ground plane, a secondground plane, a third ground plane and a fourth ground plane, whereinthe first signal line is positioned between the first ground plane andthe second ground plane and wherein the second signal line is positionedbetween the third ground plane and the fourth ground plane.
 33. Theflexible printed circuit board of claim 29, further comprising: A firstdielectric layer and a second dielectric layer, the first signal lineand the second signal line being positioned between the first dielectriclayer and the second dielectric layer.
 34. A method for manufacturing aflexible printed circuit board, comprising: providing a conducting layerincluding a first signal line and a second signal, the first signal linehaving a first physical length and a first electrical length and thesecond signal line having a second physical length and a secondelectrical length, adjusting the physical length of the first signalline to be different from the physical length of the second signal linesuch that a difference between the first electrical length and thesecond electrical length is less than one electrical degree.
 35. Themethod of claim 34, wherein the physical length of the first signal linebeing different from the physical length of the second signal line suchthat a difference between the first electrical length and the secondelectrical length is less than one-half of an electrical degree.
 36. Themethod of claim 34, wherein the physical length of the first signal linebeing different from the physical length of the second signal line suchthat a difference between the first electrical length and the secondelectrical length is less than one-quarter of an electrical degree. 37.The method of claim 34, wherein the conducting layer includes: a firstground plane, a second ground plane, a third ground plane and a fourthground plane, the method further comprising: positioning the firstsignal line between the first ground plane and the second ground plane;and positioning the second signal line between the third ground planeand the fourth ground plane.
 38. The method of claim 34, furthercomprising: providing a first dielectric layer and a second dielectriclayer; and positioning the first signal line and the second signal linebetween the first dielectric layer and the second dielectric layer.